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The present invention relates to integrated circuit memory devices, and specifically to wordline decoders within such devices. Improvements in speed, device area, functionality, test cost, and power consumption are ever important to this field of design.
Semiconductor memory devices are often fabricated in complementary metal oxide semiconductor process, a technology using devices of n-type conductivity and devices of p-type conductivity on the same semiconductor substrate. The current invention discloses a device needing fewer components than prior-art designs to protect against parasitic latch-up, a hazard inherent in this technology.
Substantially half the cost of a high-capacity memory device is due to test and repair needed to guarantee proper operation. The current invention discloses a device and method which significantly speed factory test operations, and which provide improved speed, power consumption and device size.
FIG. 1 shows a prior-art wordline decoder as taught by US Pat. No. 6,130,855 xe2x80x9cLatching wordline driver for multi-bank memory,xe2x80x9d issued Oct. 10, 2000 to Keeth. In FIG. 1, clamping transistor 162 is present only to prevent process parasitic latch-up, a condition due to turnon of an unintended parasitic device in complementary metal oxide semiconductor process structures. The condition can draw more current than normal design maximum current and can make the device non-functional until power is removed. The condition can occur in the circuit of FIG. 1 if a drain-to-substrate diode in transistor 164 should become forward biased. When a design has two or more separate voltage supplies, at power-up the supplies will come up to their full voltage at different times. If VCC supply comes up to full voltage before VPP supply, VCC voltage could couple to the drain of transistor 164 while VPP voltage is substantially less than VCC. Since VPP voltage is coupled to the substrate of transistor 164, forward bias of its drain-to-substrate diode would be established by such an event and the resulting current flow can initiate latch-up. Transistor 162 prevents the drain voltage of transistor 164 from exceeding VPP because transistor 162 is off, due to the coupling of a gate of transistor 162 to VPP, whenever VCC voltage exceeds VPP voltage.
Transistor 162 also forms part of the signal path for driving wordline WL high. In order to drive WL high, a logic low voltage level on node LPH* must couple to node 174 through transistor 162, overpowering transistor 164 and pulling node 174 low to turn on pullup driver transistor 166, which then pulls WL high. During this speedcritical transition, the impedance of transistor 162 causes the disadvantage of slowing the circuit without benefiting circuit operation.
In order to counter the slowing effect of transistor 162, four transistors 150A-150D in series between transistor 162 and node LPH* must all be larger in size than they would be if transistor 162 were not xe2x80x98in the way.xe2x80x99 The presence of transistor 162 in the prior-art design of FIG. 1 slows the performance and increases chip size, not just by its own area, but also by the increased size of other transistors. Since every WL has transistor 162, the size penalty associated with transistor 162 is multiplied by the number of rows in the memory array. The size penalty is a disadvantage of the FIG. 1 design.
Also in FIG. 1, the high-to-low transition of wordline WL has a further disadvantage. Transistor 170 overpowers transistor 166 in order to force the transition, which draws useless crossing-current directly from VPP to VSS while both transistors are on. The sequence is as follows. Initially, transistor 166 is turned on, pulling WL high. Input LPH* goes high, turning on transistor 170, starting the crossing-current flow. Transistors 166 and 170 are both on at this point. Transistor 170 then pulls WL low against the pullup of transistor 166. When WL has been pulled low, transistor 160 turns off and transistor 164 turns on, which then pulls up the gate of transistor 166, cutting off the crossing-current only when the gate voltage of transistor 166 has moved within a p-type transistor threshold voltage of VPP supply.
Transistor 166 must be strong enough to quickly pull up the capacitive load of wordline WL, which is very large because typically one thousand or more transistor gates are attached to WL. Because transistor 170 must be strong enough to overpower transistor 166 rapidly while also pulling the very large wordline capacitive load low, transistor 170 requires several times more chip area than necessary. Oversizing transistor 170 places more capacitive load on the LPH* node than necessary, due to increased gate capacitance of transistor 170 arising from its larger size, causing the circuits that drive LPH* to be larger than necessary to obtain high speed, and to use more power than necessary in performing the switching. The area and power penalties of transistor 170 in this design are multiplied by the number of rows in the array as every row has this transistor. The gate-capacitance power penalty for oversizing transistor 170 is paid on both rising and falling transition of WL. Failure to turn off transistor 166 during WL falling transition uses more power than necessary because all the current conducted by the pullup during this transition is used only to fight the needed transition. There is a power penalty because transistor 166 is connected to the high voltage supply VPP, which causes more wasted crossing-current to flow through transistor 170 because VPP is significantly higher VCC, than would be the case if transistor 166 used voltage supply VCC. Wasted VPP current causes extra wasted current in the charge pump which keeps VPP high because the efficiency of the charge-pump itself is at most only 50%. WL turnoff is slower than necessary due to the contention between active pullup and pulldown transistors. Thus this prior art design is slowed unnecessarily, and it consumes more chip area and power than necessary.
Further, the FIG. 1 design has a control signal, NSA*, driving a decoder input. Careful reading of this patent shows that NSA* is the inverse of sense-amplifier enabling signal NSA: when the sense-amplifier is enabled by NSA being high, the wordline decoder is disabled by NSA* being low. Coupling the NSA* signal to decoder input as shown prevents the FIG. 1 design and method from implementing high-speed functions to aid factory test and repair. This is a disadvantage of the FIG. 1 design.
FIG. 2 shows a prior-art wordline driver as disclosed by U.S. Pat. No. 6,324,088, issued Nov. 27, 2001 to Keeth, et al. This circuit has the same as the FIG. 1 design, with crossing-current due to contention of wordline driver transistors, and with latch-up control that negatively impacts speed, power, and area. Further, the FIG. 2 design does not have wordline latching, and so cannot implement high-speed functions to aid factory test and repair.
FIG. 3 shows a prior-art wordline driver as taught by U.S. Pat. No. 6,226,218 xe2x80x9cRow decoder driver for semiconductor memory device,xe2x80x9d issued May. 1, 2001 to Kim. The design of FIG. 3 fails to address an issue of process parasitic latch-up inherent in high-voltage driver design. Unless the design precludes process parasitic latch-up, the circuit can become locked into an unusable condition by excessive latch-up current. The FIG. 3 design does not have wordline latching, and so cannot implement high-speed functions to aid factory test and repair. These are disadvantages in the FIG. 3 design.
A wordline decoder device for multi-section memory is disclosed, providing a new combination of optimized speed, area, and power, with self-latching wordline signal and exclusion of process parasitic latch-up.
Objects of the current invention are:
(a) Implementing protection against process parasitic latch-up using fewer transistors than prior art, while avoiding latch-up control devices in a critical speed path,
(b) Initiating wordline transitions by overpowering only low-power feedback transistors, not high-power driver transistors, and
(c) Provision of self-latching capability for the signal on the wordline node.
Advantages of the current invention include
(a) a dramatic reduction in the number of transistors used to protect against process parasitic latch-up, providing significant savings in device area and power over prior art designs,
(b) speed improvements over prior art by relocating transistors used to protect against process parasitic latch-up so that they are not in a speed-critical path,
(c) area improvements over prior art by relocating transistors used to protect against process parasitic latch-up so that they are not in a speed-critical path, because no components need to be oversized to maintain device speed,
(d) speed, power, and area improvements over prior art by avoiding any need to overpower large driver transistors during wordline switching, and
(e) a device with self-latching output wordline that supports a new high-speed method for copying data from row to row during factory test and repair.